NCP1603D100R2G【PDF 20/30 页】IC CTLR PFC/PWM COMBO 16-SOIC

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Sheet目录45

16页 17页 18页 19页 [20页]21页 22页 23页 24页

NCP1603

http://onsemi.com

5.6 V

12.6 V

7.7 V

CC2

Startup current source

charging the V

capacitor

Startup circuit turns off

when V

CC2

is 12.6 V

Circuit sleeps when

CC2

is below 7.7 V

Maximum drain current

is limited to 1 / R

CS2

Startup circuit turns on

when V

CC2

is 5.6 V

Switching starts when

CC2

reaches 12.6 V

Peak drain current follows

a 2.5 ms softstart envelope

Switching is missing

in every two V

hiccup cycles

featuring a double hiccup

Figure 53. Timing Diagram of Fault Condition

time

Figure 53 illustrates the timing diagram of V

CC2

and the

secondstage drain current I

in fault condition. The V

drops because output voltage collapses. When V

drops

below V

CC(off)

(7.7 V typical), the Drive Output signal

disappears and the V

continues to drop. When bias

voltage V

drops to V

CC(latch)

(5.6 V typical), the startup

current source activates and charge up the V

until V

reaches V

CC(on)

(12.6 V typical). The internal 2.5 ms

softstart activates after V

reaches V

CC(on)

(12.6 V

typical). The peak drain current follows its 2.5 ms

envelope. The power supply dissipates some power due to

the switching signal of Out2 and waits for possible

autorecovery of operation when the fault is cleared.

As shown in Figure 53, NCP1603 has a double hiccup

feature that allows the drain current in every two V

hiccup cycle in fault condition. The double hiccup

feature offers fewer power dissipation during fault

condition comparing to single hiccup.

If the fault is cleared (V

FB2

< 3.0 V

) and V

remains

above V

CC2(off)

(7.7 V typical), the circuit will resume its

operation. Otherwise, the V

will continue this

12.67.75.612.6 V hiccup mode until the fault or bulk

voltage is cleared.

Standby Condition

The output voltage rises up excessively in standby

condition and the V

FB2

drops. A set point of 25% of the

maximum of V

FB2

(i.e., 3.0 V) is defined to be the standby

threshold. Hence, the standby threshold is V

stby

= 25% ?/DIV>

3.0 V = 0.75 V.

FB2

125 ms

delay

Leave standby

0.75 V / 1.25 V

FB2

enable Vaux /

Standby

disable

Vaux/

PFC

Section

Figure 54. Block Diagram and Timing Diagram of

Standby Detection

FB2

aux

1.25 V

0.75 V

125 ms

aux

stops when V

FB2

below 0.75 V and cannot go

above 1.25 V for 125 ms

aux

restores when

FB2

goes above 1.25 V

time

PFC Section

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